We present experimental results of superconducting voltagehyphen;state complementary output switching logic gates operating 10 Gb/s and 2hyphen;bit encoder circuits clocked at 5ndash;8 Gb/s. The logic gates and circuits were designed using a Monte Carlo optimization process so that they have a high theoretical yield at 5ndash;10 Gb/s in spite of existing Josephson junction process variations. copy;1996 American Institute of Physics.
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