Anomalous capacitancehyphen;voltage behavior due to dopant segregation and carrier trapping in Ashyphen;implanted polycrystalline silicon and silicided polycrystalline silicon gates

摘要

This letter discusses the anomalous capacitancehyphen;voltage characteristics of Ashyphen;implanted polycrystalline silicon and amorphous Si gate metalhyphen;oxidehyphen;semiconductor (MOS) structures fabricated with and without a TiSi2layer. The effects of gate bias and process parameters such as annealing temperature, process details of silicide formation, and polycrystalline silicon grain microstructure on the capacitancehyphen;voltage (Chyphen;V) characteristics have also been studied. It is shown that insufficient As redistribution at 800thinsp;deg;C, coupled with carrier trapping at polycrystalline silicon grain boundaries and dopant segregation in TiSi2, causes depletion effects in the polycrystalline silicon gate and in turn, the anomalousChyphen;Vbehavior. The depletion tends to increase the lsquo;lsquo;effectiversquo;rsquo; gate oxide thickness and thereby degrade MOS device performance. Higher temperature anneals (ge;900thinsp;deg;C) are sufficient to achieve degenerate doping in the polycrystalline silicon gates and avoid the depletion effects.