Dynamic reconfiguration is an attractive technology for its computation speed comparable to that of custom hardware and its flexibility comparable to that of a general purpose computer. In this paper, scheduling data flow graphs onto dynamically and partly reconfigurable devices is treated. Since the spatial and temporal region occupied by each reconfigured module forms a cube, there are much similarities between the scheduling on dynamically and partly reconfigurable devices and packing cubes into 3D space. Based on this observation, we propose a coding scheme, constrained sequence quintuple, which represents both temporal scheduling of module reconfigurations and task executions, and spatial placement of reconfigured modules by five permutations of module (or task) names. Exploration of the solution space constructed by our constrained sequence quintuple by Simulated Annealing is demonstrated using 5th order elliptic filter example. The experimental results show us higher potential of dynamically/partly reconfiguration not only in its flexibility but also in reducing wire length and congestion.
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