Cell placement for Very Large Scale Integrated circuits (VLSI) based on a standard-cell approach consists of global and detailed placements. This global placement determines an approximate cell position and may have some effects to the final result of detailed placement. As far as we can know, there is no reference that the accuracy of a cell position at the stage of global placement was sufficiently studied. Then we define the approximate cell position as a unit of the width of placement slot in the optimization process of Simulated Annealing (SA), using the cost function of a total wire length. Thus, we try to find the final costs in details by the computer experiments using 8 benchmark circuits with 12,000～69,000 cells. We can conclude that the final cost of the total wire length reaches to the minimum value with the optimized slot width, which is around {2.5× (average cell width)}. Although the SA implementations are done using the values of 0.92 to 0.97 as temperature parameters of cooling schedule, we can get the almost same slot widths and final costs. In this paper, we will discuss the above experiment results and influences to the final costs due to the optimized slot width.
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