3.5 Gbps CMOS/SIMOX transceiver with limiting amplifier

摘要

A half-rate PLL circuit and a SOI depletion-layer guard ring were developed to reduce cross-talk noise from digital circuits to analog circuits via substrate. This provides total integration of optical transceiver functions: multiplexer/demultiplexer, PLL, CDR, 8B/10B encoder/decoder, word aligner with limiting amplifier and laser driver. One-chip transceiver fabricated with 0.2μm CMOS/SIMOX process showed 3.3× speed of 3.5 Gb/s with a conventional one and low-power consumption of 450 mW at 2.0Gb/s operation.