A Channel-based Communication/Synchronization Model for SW-HW Multitasking on Dynamically Partially Reconfigurable FPGAs

摘要

Dynamically Partially Reconfigurable (DPR) FPGAs allow for implementation of a concept of SW-HW multitasking where flow of execution run on CPU and reconfigurable hardware. This paper presents a channel-based communication model tailored for such systems. The channels are Abstract objects with unique and statically assigned IDs, passed as a parameter to channel access API calls. Physically, they are divided into master and slave parts located either in SW or dynamically reconfigured with the HW task, which allows for point-to-point inter-task communication, its optimizations between a given pair of tasks and decreases the overall logic utilization in the system.