A 3 micron BiCMOS IC technology has been proposed by combining Bipolar and basic CMOS structures using the PMOS, 5 micron deepN-Well as the collector and introducing an additional masking level forP- base region. TheP- base is about 1.6 micron deep and has a doping level of more than 1016atoms/cm3. The CMOSN+source/drain ion implantation step has been used to form the emitter and collector contact regions of the bipolar structure. Similarly, the CMOSP+source/drain ion implantation step served to create a bipolarP+base contact to minimize the base series-resistance. The paper presents a non-epitaxial and fully-implanted BiCMOS technology-architecture represented by 11 masks process. The process steps have further been simulated by using SUPREM-II and SEDAN programmes for impurity profiles, various junction depths and electrical performance of the CMOS and Bipolar parts of the BiCMOS device. The device simulator (SEDAN) takes the impurity profile generated by the process simulator (SUPREM-II). The MOS simulator (MINIMOS) has been used to study the MOS device characteristics. The simulated results along with process file are also shown in the paper.
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