Scheduling algorithm for terabit packet switch using queuing state information

摘要

The Input-and-Output Buffer switch architecture is adequate for large-scale packet switches. However, increase of port speed and port number restrict scheduling processing time that is required to decide the combination of input ports and output ports. In this paper, we introduce parallel processing block switch architecture to solve above problem and suggest scheduling algorithm using queuing state information for this switch architecture. We evaluate effectiveness of this scheduling algorithm through computer simulation.