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An Area Efficiency Hybrid Decoupling Scheme for Charge Pump Noise Suppression in Non- volatile Memory

机译:An Area Efficiency Hybrid Decoupling Scheme for Charge Pump Noise Suppression in Non- volatile Memory

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摘要

An area efficiency hybrid decoupling scheme is proposed to suppress the charge pump noise during F-N tunneling program in nonvolatile memory (NVM). The proposed scheme is focused on suppressing the average noise power in frequency domain aspect, which is more suitable for the program error reduction in NVMs. The concept of active capacitor is utilized. Feed forward effect of the amplifier is firstly considered in the impedance analysis, and a trade-off relation between in-band and out-band frequency noise decoupling performance is shown. A fast optimization based on average noise power is made to achieve minimum error in the F-N tunneling program. Simulation results show very stable output voltage in different load conditions, the average ripple voltage is 17 mV with up to 20 dB noise-suppression-ratio (NSR), and the F-N tunneling program error is less than 5 mV for a 800 μs program pulse. A test chip is also fabricated in 0.18/μm technology. The area overhead of the proposed scheme is 2. The measurement results show 24.4 mV average ripple voltage compared to 72.3 mV of the conventional one with the same decoupling capacitance size, while the noise power suppression achieves 15.4 dB.

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