Wave pipeline technique is one of the techniques in the world of CMOS technology targeted for low power consumption in microprocessor designs. This paper shows a clear logic for the experimental verification of applying the wave-pipeline technique for low power consumption, even though it is quite uncertain whether the wave pipeline technique is suitable for CMOS technology or not. First we describe here the power consumption of the execution part of the microprocessor that represents the multifunctional circuit. Next we discuss the contribution of wave-pipelining in such multifunctional circuit for low power consumption.
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