We have developed the 4Mb 1 T1C FeRAM device technology using 0.25 μm design rules, which is fully compatible with CMOS logic. This consists of three key technologies: a diffusion barrier and an oxidation barrier to W-plug, low thermal budget process for SrBi{sub}2Ta{sub}2O{sub}9 (SBT)-capacitors and no via contact cell scheme.
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