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首页> 外文期刊>IEICE Transactions on fundamentals of electronics, communications & computer sciences >Design Of An Area-efficient And Low-power Noc Architecture Using A Hybrid Network Topology
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Design Of An Area-efficient And Low-power Noc Architecture Using A Hybrid Network Topology

机译:Design Of An Area-efficient And Low-power Noc Architecture Using A Hybrid Network Topology

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摘要

This paper proposes a novel hybrid NoC structure and a dynamic job distribution algorithm which can reduce system area and power consumption by reducing packet drop rate for various multimedia applications. The proposed NoC adopts different network structures between sub-clusters. Network structure is determined by profiling application program so that packet drop rate can be minimized. The proposed job distribution algorithm assigns every job to the sub-cluster where packet drop rate can be minimized for each multimedia application program. The proposed scheme targets multimedia applications frequently used in modern embedded systems, such as MPEG4 and MP3 decoders, GPS positioning systems, and OFDM demodulators. Experimental results show that packet drop rate was reduced by 31.6 on the average, when compared to complex network structure topologies consisting of sub-clusters of same topology. Chip area and power consumption were reduced by 16.0 and 34.0, respectively.

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