机译:On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST
Kyushu Inst Technol, Iizuka, Fukuoka 8208502, Japan;
LIRMM, F-34095 Montpellier, France;
Univ Connecticut, Storrs, CT 06296 USASynTest Technol Inc, Sunnyvale, CA 94086 USA;
at-speed scan-based logic BIST; capture power safety; masking; IR-drop; transition delay fault; long sensitized path;