A variable drivability (VD) output buffer for the system in a package (SIP) and high frequency wafer test

摘要

A System In a Package (SIP) is another candidate of future embedded system chips against the System On a Chip (SOC). The SIP has chip intra connections, which have small IO load. On the other hand, the high frequency wafer test has large IO load caused by probe, Hi-Fix and coaxial cable. This paper makes these incompatible load problems clear and propose new output buffer to overcome them. A new variable drivability (VD) output buffer can provide the optimum driving ability for both the SIP intra-connection and the high frequency (over 100MHz) wafer test. This proposed output buffer realizes new SIP test flow containing high frequency wafer test and reduction of the total test cost of embedded DRAM chip by 35 compared with the conventional SIP test cost.