A Power and Delay Ontimization Method Using Input Reordering in Cell-Based CMOS Circuits

摘要

We present a method for power and delay op- timization by inputreordering. We observe that the reorder- ing has a significant effecton the power dissipation of the gate which drives the reordered gate.This is because the input ca- pacitance depends on the signal valuesof other inputs. This property, however, has not been utilized forpower reduction. Previous approaches focus on the reduction of thepower dissi- pated by internal capacitances of the reordered gate. Wepropose a heuristic algorithm considering the total power consumed inthe driving gate and the reordered gate. Experimental results using30 benchmark circuits show that our method reduces the powerdissipation in all the circuits by 5.9 on average. There is a pos-sibility that power dissipation is reduced by 22.5 maximum. In thecase of delay and power optimization, our method reduces delay by 6.7and power dissipation by 5.3 on average.