A Parallel Median Filter with Pipelined Scheduling for Real-Time 1D and 2D Signal Processing

摘要

In this paper, we propose a fast algorithm to realize parallelmedian filter for processing 1-D and 2-D signal. In the proposedpipelined architecture, m-passes are employed for filtering signalwhile word resolution is m bits. One pass employs one processingelement (PE), and the number of Pes is independent of the number ofsamples. Therefore, we only need m Pes for real-time operation. With8-bits resolution, the system gate-count is less than 5k.