In order to realize high-speed and flexible image processing, hardware implementation of complicated processing parts is essential as well as using software on PCs. VLSI implementation using FPGAs achieves lower development cost than using ASICs. It also makes it possible to design the system with high flexibility because it can implement specialized processing to supply the demand for users. Our IPs developed for binary and gray-scale image processing consist of 19 parts. They calculate various characteristic parameters of figures included in the image: perimeters, areas, positions of the center of gravity, Ferct's diameters, histograms of intensity, etc. Our IPs can also implement various image processing: dilation/erosion, labeling, projection on X/Y-axes, contrast conversion, 3×3 spatial filters, affine transforms, resistive-fuses networks, etc. Our IPs operated at a clock frequency of 40 MHz when they were implemented on an Altera FPGA (EPF10K5OSTC144-3). We applied our IPs to a cereal-grain inspection system, and reduced processing time by 50.
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