SIRENA: A CAD ENVIRONMENT FOR BEHAVIOURAL MODELLING AND SIMULATION OF VLSI CELLULAR NEURAL NETWORK CHIPS

摘要

This paper presents SIRENA, a CAD environment for the simulationand modelling of mixed-signal VLSI parallel processing chips based oncellular neural networks. SIRENA includes capabilities for: (a) thedescription of nominal and non-ideal operation of CNN analoguecircuitry at the behavioural level; (b) Performing realisticsimulations of the transient evolution of physical CNNs includingdeviations due to second-order effects of the hardware; and, (c)evaluating sensitivity figures, and realize noise and Monte Carlosimulations in the time domain. These capabilities portray SIRENA asbetter suited for CNN chip development than algorithmic simulationpackages (such as OpenSimulator, Sesame) or conventional neuralnetworks simulators (RCS, GENESIS, SFINX), which are not oriented tothe evaluation of hardware non-idealities. As compared toconventional electrical simulators (such as HSPICE or ELDO-FAS),SIRENA provides easier modelling of the hardware parasitics, asignificant reduction in computation time, and similar accuracylevels. Consequently, iteration during the design procedure becomespossible, supporting decision making regarding design strategies anddimensioning. SIRENA has been developed using object-orientedprogramming techniques in C, and currently runs under the UNIXoperating system and X-Windows framework. It employs a dedicatedhigh-level hardware description language: DECEL, fitted to thedescription of non-idealities arising in CNN hardware. This languagehas been developed aiming generality, in the sense of making norestrictions on the network models that can be implemented. SIRENA ishighly modular and composed of independent tools. This simplifiesfuture expansions and improvements. Copyright