We propose a system architecture which shorten the LSI design period. Hard-wired logics are replaced by small CPUs and ROMs which are specialized to the processing. The bug of specification can cope with it by correction of software ROM, and does not influence the layout design of a processor. Therefore, a hardware and a software design can be simultaneously done on from early stages of a design. We designed a processor which lowered hardware cost as the first phase of the proposed architecture. The instruction set is compatible with SH-2 of Hitachi. Consequently, area of processor is smaller than conventional processors. This design was performed using RTL description of SystemC. Although there was a difference in description with the design using the conventional HDL, it turns out that sufficient simulation speed is obtained.
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