A tight clock synchronization technique for multiprocessor systems

摘要

AbstractIn this paper we present a tight clock synchronization scheme for large‐scale multiprocessor systems. the proposed scheme consists of two symmetric loops for transmission of the master clock signals and askew cancellation circuit(SCC) for each node to be synchronized to the master clock. Each clocking signal generated by the master clock source is replicated into two identical copies and the twin signals are transmitted on two symmetric loops in opposite directions. to cancel the time skew between them caused by the transmission network, the time difference between the two clocks' arrival times at any node is first measured and stored in each node. Then each of the leading signals received from the loop in a node is issued to its functional units after the signal is delayed by half the measured phase difference. It is shown that the system clock skew can be made independent of the delay of the transmission lines by the proposed scheme at a low hardware cost.To explore the feasibility of the proposed scheme, the SCC is designed with a combination of programmable delay element arrays and a phase detector. the floor‐plan of the SCC is implemented by the MAGIC VLSI lay‐out tool based on MOSIS CMOS 2 μm technology and extensively sim