Double detection is known as a method of fault simulation that can remove all redundant test vectors in a test set for a combinational circuit. Though double detection does not require much memory space, runtime increases with the number of test vectors because fault simulation is repeated. In this paper, we propose a procedure to accelerate double detection, in which intermediate data obtained during the first fault simulation are used and the number of faults targeted is reduced in the second fault simulation. Experimental results for ISCAS benchmark circuits show that the proposed procedure could reduce runtime of double detection to half of the original procedure.
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