Design of a Field-Programmable Digital Filter Chip Using Multiple-Valued Current-Mode Logic

摘要

This paper presents a Field-Programmable Digital Filter (FPDF) IC that employs carry-propagation-free redundant arithmetic algorithms for faster computation and multiple-valued current-mode circuit technology for high-density low-power implementation. The original contribution of this paper is to evaluate, through actual chip fabrication, the potential impact of multiple-valued current-mode circuit technology on the reduction of hardware complexity required for DSP-oriented programmable ICs. The prototype FPDF fabrication with 0.6μm CMOS technology demonstrates that the chip area and power consumption can be reduced to 41 and 71, respectively, compared with the standard binary logic implementation.