For data flow graphs with conditional branches most of conventional pipelined scheduling methods have not been able to obtain optimal schedules in regard to hardware area, because they have assigned operations in each conditional branch to individual hardware units. This paper proposes a pipelined scheduling for signal-processing circuits with conditional branches. In order to minimize hardware area under the constraint corresponding to processing speed of the slowest part in a chip, our approach schedules the whole a signal processing system including the conditions and branches. First, our approach assigns operations to each control step so as to close to the same number of operations in conditional branches. Next, it closes the same number of operations in each control step to maximal number of operations. The experimental results show that our proposed approach is effective.
展开▼
