Partial logic synthesis is a method that most parts of the target circuits are fixed and the missing portions can be logic synthesized from the large numbers of selections. By modeling the missing portions with Look Up Table (LUT), the synthesis and verification problem can be formulated as Quantified Boolean Formulae (QBF). Partial synthesis works well for non-arithmetic circuits, but for integer multipliers it works only if the target circuit and the specification model to be compared are structurally very close. If the target circuit and the specification model to be compared are not close, such as the cases where implementations are gate level and the specification is just arithmetic multiplication symbol, partial logic synthesis can only work up for 12 bits integer multipliers. The reason is that the method must spend most of the time on the equivalence checking of the two circuits and it is very time consuming if the structures are not similar. Now there are interests in synthesis and verification of large size multipliers such as in cryptography. In this paper, we tried to give an improved and proposed method based on the traditional partial synthesis to speed up the process of large integer multipliers. We applied an approach named Column Wise method to do the last step of equivalence checking. The result showed that we can apply our method to 64 bits integer multipliers within 43 seconds.
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