CMOS Implementation of a Multiple-Valued Memory Cell Using Λ-Shaped Negative-Resistance Devices

摘要

In this paper, we propose the CMOS implementation of a multiple-valued memory cell using Λ-shaped negative-resistance devices. We first propose the construction of a multiple-stable circuit that consists of Λ-shaped negative-resistance devices from four enhancement-mode MOS-FETs without a floating voltage source, and connect this in parallel with a unit circuit. It is shown that the movement of Λ-shaped negative-resistance characteristics in the direction of the voltage axis is due to voltage sources. Furthermore, we propose the construction of a multiple-valued memory cell using a multiple-stable circuit. It is shown that it is possible to write and hold data. If the power supply is switched on, it has a feature which enables operation without any electric charge leakage. It is possible, by connecting Λ-shaped negative-resistance devices in parallel, to easily increase the number of multiple values.