Reducing Memory Access Stage of Pipelined CISC Processor by Self-Hazard

摘要

One of the advantages of CISC type processors is code efficiency since each instruction can contain many micro operations. On the other hand, the relatively large number of instruction execution stages of CISC processor may lead to higher cost if the processor is pipelined. In this paper a method to reduce the number of pipeline stages for CISC processors is presented where stages dedicated to memory access are eliminated by self-hazard technique.