A new CMOS logic circuit technology ASDL (Asymmetric Slope Differential Logic) is proposed, which is targeting two-fold speed up of conventional CMOS. ASDL handles differential signal inputs and outputs, and has a special feature of asymmetric signal transition delay of fast signal rising and slow falling, which enables very high speed signal rising propagation. ASDDL (Asymmetric Slope Differential Dynamic Logic) is a variant of ASDL and has a unique feature of "clockless dynamic logic" for higher speed operation. A 16-bit multiplier has been designed in ASDDL for 1.8 μm process and 1.8V operation. Operation time were measured in circuit simulations. An ASDDL full adder shows 55 signal delay of that of CMOS full adder. Operation time of the ASDDL 16-bit multiplier is 2.15n5, which is 66 of that of CMOS multiplier.
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