High performance 90 nm node PD SOI CMOS devices

摘要

A design for 90 nm node Partially Depleted (PD) SOI MOSFET for High-End LSI is proposed. By combination of optimized gate oxide formation, extension/halo implantation and spike annealing process for S/D activation, a drive current of 910μA/μm for NMOS and 320μA/μm for PMOS at an off current of 30 nA/μm and 1 V supply voltage has been achieved with self-heating. Moreover, 10 years HCI Life Time is also achieved for both NMOS and PMOS.