We report on the fabrication of a novel 3-D device structure, the Multi-Pillar Surrounding Gate type MOS capacitor using 0.4μm MOS technology. In order to investigate the gate oxide at the sidewall of the silicon pillar by C-V measurements, thick oxides compared with the thickness of the gate oxide are formed at both the top of the pillars and at the bottom of the trenches. The gate oxide thickness obtained by the measured capacitances is 16nm. The electrical gate oxide thickness extracted for the Multi-Pillar Surrounding Gate type MOS capacitor agrees well with the physical gate oxide thickness within 5.9 (1nm) error.
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