Problems and Solution of DSM Variability Design in 90nm Era

摘要

For 130nm LSI and Process and beyond, intar-chip variation is one of the crusial issues. Especially Clock-Skew is largely affected by the intar-chip variation. In Low-Power LSI's, reduced supply voltage results in critical design margin problems as well as leakage ones. In 90nm process, it is well recognized that reliability, variability on wafer and yield of LSI's are design matter as well as Process one, which is called DFM(Design for manufacturability). We propose a novel Test-Structure (TEG) which bridges the gap between Variability design and Fab. Process control issues.