This paper proposes a new high-level synthesis system which can synthesize low-powered system VLSIs under the constraints of area, delay, and execution time. In the proposed system, first an initial system hardware is obtained from an abstract behavioral description. Then three power reduction techniques, 1) reducing power supply voltage, 2) selecting lower power modules, and 3) applying gated clocks, are applied to it. However these power reduction techniques may increase area, delay, and/or execution time of a synthesized hardware, while they can reduce its power dissipation. In this paper, we propose a power optimization algorithm which incorporates area/delay/power estimation, in which we can obtain a synthesized hardware meeting given area/delay/power constraints. Experimental results demonstrate effectiveness and efficiency of the algorithm.
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