This paper presents a high-level test synthe- sis algorithm foroperation scheduling and data path allocation. Data path allocationis achieved by a controllability and observ- ability balanceallocation technique which is based on testability analysis atregister-transfer level. Scheduling, on other hand, is carried out byrescheduling transformations which change the de- fault scheduling toimprove testability. Contrary to other works in which the schedulingand allocation tasks are performed inde- pendently, our approachintegrates scheduling and allocation by performing themsimultaneously so that the effects of scheduling and allocation ontestability are exploited more effectively. Ad- ditionally, sincesequential loops are widely recognized to make a design hard-to-test,a complete (functional and topological) loop analysis is performed atregister-transfer level in order to avoid loop creation during theintegrated test synthesis process. With a variety of synthesisbenchmarks, experimental results show clearly the advantages of theproposed algorithm.
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