In order to easily estimate power dissipations of large CMOS logic circuits without using any CAD tools, a simple and closed expression of a short-circuit power dissipation (p{sub}s) and that of a power dissipation due to charge-discharge currents (p{sub}D) have been developed for various CMOS logic gates such as NOT, NAND, AND-NOR, etc. A number (m) of fan-outs of the driver and a number (n) of fan-outs of the given logic gate were used for unknown rise and fall times, and load capacitors, respectively. The calculated power dissipation of a 0.13-μm CMOS adder with these expressions was almost the same as that with SPICE. A self-controllable-voltage-level (SVL) circuit was also developed. This SVL circuit can drastically reduce standby leakage power of CMOS logic circuits with minimal overheads in terms of chip area and speed. Furthermore, it can also be applied to memories and registers, because such circuits fitted with SVL circuits can retain data even in the stand-by mode. The stand-by power of a 512-bit memory cell array incorporating an SVL circuit for a 0.13-μm SRAM was 66.1 nW, 2.3 of that of an equivalent conventional memory-cell array. The read-access time of this SRAM was only 0.7 slower than that of the equivalent conventional SRAM.
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