This paper introduces the design of a parallel and concurrent LSI system for countious hidden Markov models (CHMM). The new design can realize a speech recognition system with high performance and real time response. Recently the technologies of speech recognition methods and circuit design have considerably progressed and consequently a speech recognition chip has been tried to be developed with a low-power and small-size circuits. However, many issues still result in the large computation time and the high data accuracy. Therefore, this report proposes a new parallel VLSI architecture for a speech recognition technique with floating-point-units (FPU) and parallel/pipeline mechanism. The speech recognition VLSI is designed in 0.35μm CMOS process and can be clocked at 70MHz.
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