Booth selector consumes relatively large part of area and power dissipation in a Wallace-tree multiplier. This report proposes new Booth selector algorithms, Tamura method and Tei method. The former requires only 9 transistors for generating each partial product bit using pass-transistor logic SPL, and useful when area constraint is dominating. The latter requires 12 transistors for generating each partial product bit using transmission gate, and usable for low-voltage operation. In addition, it requires only 6 inputs for one partial product bit, which is effective for reducing congestion.
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