This report introduces the ASIP Meister that is a development environment for Application Specific Processors. Using ASIP Meister, design time of ASIPs becomes much shorter than those of conventional processor deign methods. ASIP Meister enables designer to design pipeline processors without describing the precise pipeline controls of a processor. In this report, the outline of ASIP Meister and the design flow using ASIP Meister are introduced first. At each design step, designs proceed with appropriate inputs or selecting items from lists. As a case study, several RISC processors were designed using the ASIP Meister system.
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