In the embedded system design, application specific instruction-set processors (ASIPs) which consist of application specific instructions and hardware resources are embedded to various systems. To achieve high performance and high flexibility, the pipeline architecture is often employed in ASIPs design, and the ASIP design environment, ASIP Meister, that automatically generates HDL of ASIP from micro-operation descriptions was proposed. In this paper, the resource allocation method, that allocates resources to pipeline stages of the processor with the minimum number of stages which satisfies the given maximum delay time constraint, is proposed. The proposed method searches the resource allocation, which satisfy the given maximum delay time and is the minimum number of pipeline stages for all varieties of resource allocations. Experimental results show that the proposed minimizing the number in short time under the delay constraint. five seconds confirming effectiveness of the method.
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