For high-speed and low power floating-point dividers, both a pre-scaling method and a high-radix nonrestoring divide method have been studied. Circuit volumes and processing speeds of both a radix-4 significant circuit and a radix-8 significant circuit, which would be used in a 64-bit floating-point divider, were examined. The radix-8 significant circuit was much faster than the radix-4 significant circuit, but number of FETs of the former was 74.3K, that is 1.5 times larger than that of the later. By reducing number of adders due to simplifying processing algorithm the FET counts of the former was reduced to 31.9 K that was only 64 that of the later. A 32-bit floating-point divider was designed employing both the pre-scaling method and the newly developed radix-8 significant circuit and using 0.5-μm CMOS technologies. The latency was 14 machine cycles. It operated at 50 MHz on 3.3 V consuming 43.53 mW that was obtained by SPICE simulation.
展开▼
