This paper proposes a non-scan DFT method for hierarchical testability of a register transfer level data path using control vector sequences generated by an original controller. In hierarchical test generation, a test plan for each module in the data path is generated. The test plan consists of a control vector sequence that can justify any value to the inputs of the module under test from some primary inputs and can propagate its output value to a primary output. In order to generate a control vector sequence for a test plan from the original controller, we extract an extended test control data flow graph from the data path and the controller. In our proposed method, the area overhead for a hierarchically testable data path is smaller than our previous work since the area overhead for the test controller to supply such test plans to the data path is small. Furthermore, our proposed method can achieve 100 fault efficiency and at-speed testing.
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