机译:Overview of Board-Level Solder Joint Reliability Modeling for Single Die and Stacked Die CSPs
Amkor Technology, Singapore 118222;
School of Mechanical and Aerospace Engineering, Nanyang Technological University, Singapore 639798;
Chip-scale packages (CSPs); critical solder joint locations; fatigue life; finite element analysis (FEA); modeling; single die CSPs; solder joint reliability; stacked die CSPs; system-in-package (SiP);