Design of signal word decomposed filters with reduced VLSI gate count

摘要

A new design of signal word decomposed filters (SWDFs) is proposed, Unlike the conventional method which only considers the number of full adders included in multipliers, all components implemented on VLSI are taken into account for the evaluation of filter complexity. Then the constraint that non-zero coefficients of less significant subfilter be equal to those of more significant subfilter is found to be quite effective in simplifying the structure and yet keeping the filter performance. The design is formulated as a line programming. As a result, SWDFs with reduced gate count are designed.