Reliability characterization of a 3‐mum cmos/sos process

摘要

AbstractA continuing study of advanced short‐channel CMOS/SOS arrays has been carried out at the RCA Microelectronics Center (MEC) and at RCA Laboratories, Princeton, NJ, since 1981. A technique to assess the reliability of a new process relatively quickly consists of high‐tempertaure accelerated stress testing of ICs by maintaining the temperature at 200°C, while biasing half the inputs at the positive supply voltage and half at ground. The results of these accelerated stress tests together with device analysis, were used to calculate a failure rate and to determine that time‐dependent dielectric breakdown (TDDB) is the principal failure mechanism. No mechanism unique to the CMOS/SOS technology has been ob