Very low power system LSI toward 0.1V operation - issues and solutions for low power circuit techniques

摘要

Leakage current is growing remarkably in sub-100nm era and it will prevent system LSIs to suppress the power dissipation. Such leakage current includes the sub-threshold leak and the gate-tunneling leak of MOS transistors. The leakage current will dominate the system LSIs' performance in the near future. Several low-power techniques are evaluated and issues are discussed from the view point of leakage reduction. The LSI design must become complicated when intellectual properties (IPs) are re-used for a highly functional and integrated system-in-a-package chip. Then the low-power techniques are required to be simple, unified and generalized. The power switch system corresponding to the IP design is suggested as a generalized technology. The simultaneous supply-voltage and body-bias control is discussed as a technology integration.