Design and evaluation of a floating-point 3D Euclidean norm computing circuit based on our previously proposed hardware algorithm are presented. The inputs and the output of the circuit are in IEEE-754 floating point basic format. A circuit block for aligning inputs, and one for post-normalization have been designed, as well as one for computing the mantissa part. A new method for merging the process for aligning inputs into the computation of the mantissa part is proposed. It is shown through circuit design that the proposed method reduce the whole circuit area with about 17.
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