A Neural-Greedy Combination Algorithm for Board-Level Routing in FPGA-Based Logic Emulation Systems

摘要

An approximation algorithm composed of a dig- ital neural network(DNN) and a modified greedy algorithm (MGA) is presented for theboard-level routing problem (BLRP) in a logic emulation system basedon field-programmable gate arrays (FPGA's) in this paper. For a rapidprototyping of large scale digital systems, multiple FPGA's providean efficient logic emulation system, where signals or nets betweendesign partitions embedded on different FPGA's are connected throughcrossbars. The goal of BLRP, known to be NP-complete in general, isto find a net assignment to crossbars subject to the constraint thatall the terminals of any net must be connected through a sin- glecrossbar while the number of I/O pins designated for each crossbar mis limited n an FPGA.