Architecture of IEEE802.lli Cipher Algorithms for Embedded Systems

摘要

VLSI architecture of IEEE802.lli cipher algorithms is devised dedicatedly for embedded implementation of IEEE802.1la/g wireless communication systems. The proposed architecture consists mainly of RC4 unit for WEP/TKIP and AES unit. The RC4 unit successfully adopts packed memory accessing architecture. As for the AES unit, overlapped pipeline scheme of CBC-MAC and Counter-Mode is exploited in order to conceal processing latency. The cipher core has been implemented with ISKgates in 0.18μm CMOS technology, which achieves the maximum transmission rate of IEEE802.1la/g at 60 MHz clock frequency while consuming 14.5 mW of power.