A low-power high-speed rail-to-rail class-B buffer amplifier for LCD displays of various resolutions is proposed. To archive low-power and high-speed, the buffer amplifier incorporates complementary differential input stage with positive feedback to sense the input and two comparators to control the on/off of the output stages. Only one compensation resistor is used to stabilize the circuit by forming a zero with the load capacitor. The buffer assumes little quiescent current and fast response. Simulation with HSPICE in a 0.35 μm CMOS process shows that it draws only 3.6 μA at static state. Settling times for a 3.3 V output swing to within 0.2 are 2.1 μs and 1.9 μs for the rising edge and falling edge, respectively, under a 600 pF load capacitance.
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