We have proposed and implemented all digital wireless modem using Si CMOS process. All components of the proposed modem have been utilized digital logic CMOS gates. The divided clock has been employed as a carrier of proposed all digital wireless modem. BPSK modulator can be constructed using clock divider and Ex-OR gate. BPSK demodulator can be constructed using shift-registers and Ex-OR gate. The performance of the implemented modem using FPGA has been measured. The degradation from theoretical limit of differential BPSK has been confirmed to be less than 0.6dB at the BER of 10{sup}(-3). The power consumption of the fabricated LSI using 0.25μm CMOS has been confirmed to be less than 50mW at the clock frequency of 280MHz. In this paper, we have proposed and implemented synchronization circuit for the All Digital Wireless Modem only using digital logic gates. The measured FER with the proposed circuit has been confirmed to be less than 10{sup}(-6) when the clock difference between transmitter and receiver is less than 12ppm.
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