An eFPGA Generation Suite with Customizable Architecture and IDE

摘要

From edge devices to cloud servers, providingoptimized hardware acceleration for specific applications has becomea key approach to improve the efficiency of computer systems.Traditionally, many systems employ commercial fieldprogrammablegate arrays (FPGAs) to implement dedicatedhardware accelerator as the CPU’s co-processor. However, commercialFPGAs are designed in generic architectures and are providedin the form of discrete chips, which makes it difficult tomeet increasingly diversified market needs, such as balancing reconfigurablehardware resources for a specific application, or tobe integrated into a customer’s system-on-a-chip (SoC) in theform of embedded FPGA (eFPGA). In this paper, we proposean eFPGA generation suite with customizable architecture andintegrated development environment (IDE), which covers the entireeFPGA design generation, testing, and utilization stages.For the eFPGA design generation, our intellectual property (IP)generation flow can explore the optimal logic cell, routing, andarray structures for given target applications. For the testability,we employ a previously proposed shipping test method thatis 100 accurate at detecting all stuck-at faults in the entireFPGA-IP. In addition, we propose a user-friendly and customizableWeb-based IDE framework for the generated eFPGA basedon the NODE-RED development framework. In the case study,we show an eFPGA architecture exploration example for a differentialprivacy encryption application using the proposed suite.Then we show the implementation and evaluation of the eFPGAprototype with a 55nm test element group chip design.