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首页> 外文期刊>ECS Journal of Solid State Science and Technology >Circuit Level Analysis of a Dual Material Graded Channel (DMGC) Cylindrical Gate All Around (CGAA) FET at Nanoscale Regime
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Circuit Level Analysis of a Dual Material Graded Channel (DMGC) Cylindrical Gate All Around (CGAA) FET at Nanoscale Regime

机译:Circuit Level Analysis of a Dual Material Graded Channel (DMGC) Cylindrical Gate All Around (CGAA) FET at Nanoscale Regime

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摘要

Gate-all around (GAA) device is one of the cutting-edge technologies in the present semiconductor era owing to enhanced gate controllability and scalability at the nanoscale regime. The advantages of available GAA devices can further be improved by incorporating the dual material (DM) and graded channel (GC) techniques. To make use of these advantages, this manuscript investigates for the first time, the performance analysis of DMGC cylindrical GAA (DMGC CGAA) FET and its circuit applications such as inverter, NAND, NOR, ring oscillator and 6T static random-access memory (SRAM). Through the analysis, it has been found that the I-off, SS, DIBL, and I-on/I-off ratio are enhanced by an amount of 96.93, 19.49, 51.26, and 96.98 respectively for DMGC CGAA FET when compared to single metal graded channel (SMGC) CGAA FET. Single-k (SiO2) and dual-k (SiO2+HfO2) techniques are also utilized here to analyse the device performance and dual-k recorded better performance in comparison with single-k owing to reduced off-state currents. It is noticed that delay has been reduced greatly for Inverter, NAND, and NOR by an amount of 51.93, 11.25, and 10.07 respectively for dual-k when compared to single-k DMGC CGAA FET. The frequency of oscillations for Ring Oscillator is improved by 69.7 with dual-k than single-k. Further, the obtained results of SRAM are compared with the existing literatures and noticed that the proposed DMGC CGAA FET outperforms the other works making the device a potential candidature for high performance applications.

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